1. Field of the Invention
The present invention relates to an image processing apparatus, and more specifically to a construction of an image memory and its control system for forming picture at high speed on the basis of three-dimensional image data.
2. Description of the Prior Art
In the three-dimensional image processing apparatus, frame data (i.e., color data at each pixel) and Z value data (i.e., depth data) are generated by projecting an apex of a solid body defined in a three-dimensional space onto a screen space and by rasterizing image data on the basis of the projected apex data.
Further, these data are stored temporarily in an image memory during the arithmetic process of the image processing apparatus. In this case, the frame data and the Z value data are both stored in a prepared memory.
Now, as a method of storing the frame data, there are two methods of line buffer method and frame buffer method. In the case of the three-dimensional image processing, however, the frame buffer method is usually adopted because of its advantage that the access time is long as compared with when the line buffer method is adopted. Further, in the case of this frame buffer method, two buffers are often used. In this double buffer method, two frame buffers are prepared for storing data for one picture; that is, one frame buffer is used to display image data and the other frame buffer is used to write the same image data. When used, these two frame buffer memories are switched in accordance with the refresh rate of the picture.
In the three-dimensional image processing, in order to improve the polygon rate, that is, to increase the number of the polygons displayable in a unit time, it is necessary to increase the data transfer speed to a memory. One of the methods considered to improve the data transfer speed is to widen the bit width of the memory data bus.
When one region on a screen is allocated to a memory column, since the band width can be increased, the region to be accessed once can be widened, so that the data transfer speed can be increased and thereby the pixel rate can be improved.
In this case, however, in the vicinity of the polygon edges, there exists the case where an area other than the polygon region is included in the access region. In this case, there exists a problem in that a part of the data bus is used wastefully. To reduce this wasteful use of the data bus, it is necessary to change the region to be accessed into a flexible access region.
Conventionally, a DRAM having a burst transfer mode has been sometimes used as an image memory. When this DRAM is used in interleave method, it is possible to enable a continuous access, on condition that the banks are switched whenever a page to be accessed is switched, by RAS-activating the bank to be next accessed, simultaneously when the columns arranged in a predetermined direction in the memory are accessed continuously by burst transfer. In the conventional method, however, since the addresses for both the row system and the column system are inputted through only a single system, when non-continuous columns are accessed, there exists a problem in that the succeeding bank cannot be activated. In other words, in the case where the screen is divided into a plurality of regions and further the divided region is allocated to the column in one-to-one correspondence, although the continuous access in one predetermined direction can be made on a screen conveniently, when the continuous access is made in the other direction, the access in the other direction has inevitably an overhead.
In the conventional image processing apparatus which can execute the Z buffering, the frame data and the Z value data for each pixel are usually stored in each dedicated macro cell. In this method, however, the memory capacity used for the frame data or the Z value data is limited by the respective macro cell capacity. For instance, when one of both needs a large capacity but the other of both needs a relatively small capacity, although it is possible to use the limited memory capacity effectively by using the unnecessary and remaining memory capacity as the other memory capacity, since the memory is used dedicatedly, the above-mentioned method of using the memory capacity is strictly limited.
As described above, in the prior art image processing apparatus, since the data transfer efficiency is low in the region rear the polygon edges and further since the address input is made for each row system and each column system, there exists a problem in that the memory availability is low, because the overhead access cannot be eliminated and further the frame data and Z value data are both allocated to each dedicated memory.